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HCMR (HardwareContentionMarkov.lean, Research Stack, 0 sorries) provides the hardware performance model for the chiral CRT multiplexer. Connection: - Markov self-loop probability = Sidon collision rate - Mixing rate = multiplexer throughput - Cache hierarchy (L1→L2→L3→DRAM) = TreeBraid hierarchy (leaf→node→root) - COUCH gate = contention filter (rejects high self-loop configs) HCMR measured self-loop probabilities: SUBLEQ (word): 0.823 (82.3% contention) CL AVX-512: 0.885 (88.5% contention) Ring dispatch: 0.0 (0% contention — perfectly Sidon-orthogonal) Throughput formula: base_rate × (1 - self_loop_prob) = base_rate × Sidon_pass_rate This predicts multiplexer performance: Ring dispatch (q >> 1): 4/4 channels usable (100% Sidon) Word SUBLEQ (q ≈ 1.5): 0.7/4 channels usable (18% Sidon) CL AVX-512 (q ≈ 1.0): 0.5/4 channels usable (12% Sidon) Confirms q-profile sweep finding: q > 1 = 100% Sidon = ring dispatch regime. Port plan: HCMR → formal/SilverSight/HCMR/ following pipeline-math 5-file pattern, with capstone theorem connecting Sidon pass rate to HCMR throughput. |
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| .. | ||
| AUTOPROOF_INFRASTRUCTURE.md | ||
| braid_group_action.md | ||
| BRAIDSTORM_TREEBRAID_COUCH.md | ||
| CAPABILITY_GRID_MAPPING.md | ||
| CHIRAL_BATCH_ENCODING.md | ||
| CHIRAL_CRT_MULTIPLEXING.md | ||
| COLLECTIVE_INTELLIGENCE_OPTIMIZATION.md | ||
| COMPRESSION_HONEST_FINDINGS.md | ||
| CONSERVATION_LAW_CORRECTION.md | ||
| FIXEDPOINT_BRIDGE_DESIGN.md | ||
| GERVER_SIDON_DESIGN.md | ||
| HCMR_CRT_MULTIPLEXER.md | ||
| INVARIANT_COMPUTATION_GEOMETRY.md | ||
| iteration_dag.md | ||
| iteration_regime.md | ||
| MERGED_O1_TRANSFORM.md | ||
| NEXT_STEPS_PLAN.md | ||
| O1_TRANSFORMS.md | ||
| OCTAGON_PRINCIPLE.md | ||
| PRIME_SIDON_NEGATIVE_RESULT.md | ||
| REACTION_PRIMES.md | ||
| sidon_preservation_creation.md | ||
| SIDON_SOFA_COLORING.md | ||
| SIDON_SOFA_COLORING_REVIEW.md | ||
| SLOS_SIDON_VERIFICATION_RECEIPT.md | ||
| TOROIDAL_POLOIDAL_REFINEMENT.md | ||
| unified_crt_torus_dag.md | ||