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https://github.com/allaunthefox/SilverSight.git
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allaun
64e54d937d
Test harnesses added for all remaining AVM ISA ports: - C (9 tests): arithmetic, saturation, comparison, overflow, control flow, locals - C++ (9 tests): same test suite with std::optional-based error handling - Scala (9 tests): functional style with Option return - Fortran (4 tests): add, div, saturation, control flow (minimal Fortran test) - Octave/MATLAB (4 tests): basic operations test Milestone: 10/12 ports have test harnesses. Coq still pending.
80 lines
2.7 KiB
Scala
80 lines
2.7 KiB
Scala
// AVM ISA v1 — Scala Test Harness
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import silversight.avm.AVM._
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import silversight.avm.AVM
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object TestAVM {
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val QS = Q16Scale
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def check(cond: Boolean, msg: String): Unit = {
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if (cond) println(s" ✅ $msg")
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else println(s" ❌ $msg")
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}
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def test_basic_add(): Unit = {
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val prog = Vector(PushQ16(5 * QS), PushQ16(3 * QS), Primitive(AddSatQ16), Halt)
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val s = run(initState(), prog, 100).get
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check(s.stack.head.i == 8 * QS, "basic_add: 5 + 3 = 8")
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}
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def test_div_q16(): Unit = {
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val prog = Vector(PushQ16(3 * QS), PushQ16(5 * QS), Primitive(DivSatQ16), Halt)
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val s = run(initState(), prog, 100).get
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val exp = (3 * QS) / 5
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check(s.stack.head.i == exp, "div_q16: 3/5 = 0.6")
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}
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def test_saturation(): Unit = {
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val prog = Vector(PushQ16(AVMClampMax - 1), PushQ16(2), Primitive(AddSatQ16), Halt)
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val s = run(initState(), prog, 100).get
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check(s.stack.head.i == AVMClampMax, "saturation: max-1+2 = max")
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}
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def test_v6_lt(): Unit = {
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val cases = Seq((-5*QS, -3*QS, true), (-3*QS, -5*QS, false),
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(5*QS, 3*QS, false), (3*QS, 5*QS, true), (-1*QS, 2*QS, true))
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cases.foreach { case (a, b, exp) =>
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val prog = Vector(PushQ16(a), PushQ16(b), Primitive(LtQ16), Halt)
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val s = run(initState(), prog, 100).get
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check(s.stack.head.b == exp, s"v6_lt($a,$b) = $exp")
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}
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}
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def test_type_mismatch(): Unit = {
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val prog = Vector(PushBool(true), PushQ16(QS), Primitive(AddSatQ16))
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val s = run(initState(), prog, 100)
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check(s.isEmpty, "type_mismatch: rejected")
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}
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def test_div_by_zero(): Unit = {
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val prog = Vector(PushQ16(QS), PushQ16(0), Primitive(DivSatQ16))
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val s = run(initState(), prog, 100)
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check(s.isEmpty, "div_by_zero: rejected")
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}
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def test_stack_overflow(): Unit = {
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val prog = Vector.fill(AVMMaxStack + 1)(PushQ16(0: Int))
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val s = run(initState(), prog, 10000)
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check(s.isEmpty, "stack_overflow: rejected")
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}
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def test_control_flow(): Unit = {
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val prog = Vector(PushBool(true), JumpIf(4), PushQ16(0), Halt, PushQ16(QS), Halt)
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val s = run(initState(), prog, 100).get
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check(s.stack.head.i == QS, "control_flow: jump_if true")
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}
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def test_locals(): Unit = {
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val prog = Vector(PushQ16(42 * QS), Store(0), Load(0), Halt)
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val s = run(initState(1), prog, 100).get
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check(s.stack.head.i == 42 * QS, "locals: store+load")
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}
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def main(args: Array[String]): Unit = {
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println("AVM Scala Port — Test Harness")
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println("==============================")
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test_basic_add(); test_div_q16(); test_saturation(); test_v6_lt()
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test_type_mismatch(); test_div_by_zero(); test_stack_overflow()
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test_control_flow(); test_locals()
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println("\nAll Scala tests passed.")
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}
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}
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