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Five new formal modules, all clean rewrites (not ports from Research Stack). Based on the chiral CRT multiplexing framework. 1. HCMR.lean (Hardware Contention Markov Representation) - Self-loop probs: SUBLEQ=0.823, AVX-512=0.885, ring=0.0 - Throughput = base_rate × (1 - self_loop_prob) - Theorems: ring > SUBLEQ > AVX-512 ordering, COUCH stability - Connection: self_loop = Sidon collision rate 2. CacheSieve.lean (L0 Local Sorter Cache Admission) - 4-state machine: Stable → Rising → Unstable → Reset - Admission control + victim selection - Theorems: stable→promote, high contention→demote, COUCH evicts - Connection: COUCH gate = contention threshold filter 3. Blitter6502OISC.lean (6502 OISC Blitter) - SUBLEQ instruction semantics: M[b] := M[b] - M[a] - Blitter: 3 SUBLEQ per byte (negation trick) - Theorems: subtract semantics, branch on ≤0, ring faster than SUBLEQ - Connection: blitter is the 'word SUBLEQ' regime from HCMR 4. YangMillsPerformance.lean (Distributed Performance) - 5 layers: cache → memory → sync → compression → network - Composed throughput = base × ∏(1 - overhead_i) - Theorems: cache highest overhead, more layers = less throughput - Connection: cache overhead = HCMR SUBLEQ self-loop 5. WorkloadTestbench.lean (Virtual GPU Workload Simulation) - 5 workload types: stream, strided, random, gather, scatter - Maps workloads to HCMR ops and CacheSieve states - Theorems: stream highest throughput, random causes Reset - Connection: stream = ring dispatch, random = AVX-512 Suite composition: WorkloadTestbench (workload → op type) → HCMR (op → self-loop → throughput) → CacheSieve (contention → admit/evict) → Blitter6502OISC (concrete SUBLEQ execution) → YangMillsPerformance (distributed stack composition) All modules registered in lakefile.lean as SilverSightRRC roots. Lean v4.30.0-rc2, Mathlib dependency. Known sorries: 2 (CacheSieve.evict_prefers_reset needs List API work, YangMillsPerformance.compression_overhead_bounded needs conservation law formalization). All other theorems are complete.
182 lines
6.8 KiB
Text
182 lines
6.8 KiB
Text
/-
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CacheSieve.lean — L0 Local Sorter Cache Admission Control
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Static cache filtering: decides which cache lines to admit based on
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a 4-state machine. Pairs with HCMR for the complete cache performance
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model (admission + contention).
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Clean rewrite for SilverSight — not a port from Research Stack.
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Based on the chiral CRT multiplexing framework.
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States:
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- Stable: line is cached, low access frequency, keep
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- Rising: line is being promoted (frequency increasing)
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- Unstable: line is hot but contended (may thrash)
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- Reset: line evicted, must re-fetch
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Admission policy:
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- Stable → Rising on access
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- Rising → Unstable if contention detected (HCMR self-loop high)
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- Unstable → Reset if contention persists (COUCH gate fails)
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- Reset → Rising on re-access (re-admission)
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Connection to CRT multiplexer:
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- CacheSieve decides WHICH channels to admit (admission control)
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- HCMR models CONTENTION on admitted channels (throughput)
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- Together: complete cache performance model
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-/
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import Mathlib.Data.Real.Basic
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import Mathlib.Tactic
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namespace SilverSight.CacheSieve
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/-- Sieve state: the 4-state machine for cache admission. -/
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inductive SieveState where
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| stable : SieveState -- cached, low frequency, keep
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| rising : SieveState -- being promoted (frequency increasing)
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| unstable : SieveState -- hot but contended (may thrash)
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| reset : SieveState -- evicted, must re-fetch
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deriving Repr, DecidableEq
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/-- Cache line with sieve state and access count. -/
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structure CacheLine where
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addr : ℕ -- cache line address
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state : SieveState
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accessCount : ℕ -- number of accesses since admission
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deriving Repr
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/-- The sieve: a collection of cache lines with a capacity. -/
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structure CacheSieve where
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lines : List CacheLine
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capacity : ℕ -- max lines the cache can hold
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deriving Repr
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/-- Access outcome: did the access hit, miss, or promote/demote? -/
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inductive AccessResult where
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| hit : AccessResult -- line was stable/rising, access succeeded
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| miss : AccessResult -- line was reset/absent, must fetch
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| promote : AccessResult -- line promoted (stable→rising or reset→rising)
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| demote : AccessResult -- line demoted (rising→unstable or unstable→reset)
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deriving Repr
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/-- Contention level from HCMR (self-loop probability as Q16_16 raw). -/
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-- 0 = no contention, 65536 = fully contended
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def ContentionThreshold : ℕ := 49152 -- 0.75 × 65536 — high contention cutoff
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/-- Transition: given current state, access count, and contention, what's next?
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- Stable + access → Rising (promote)
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- Rising + low contention → Rising (stay, accumulating heat)
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- Rising + high contention → Unstable (demote)
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- Unstable + high contention → Reset (evict)
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- Unstable + low contention → Rising (recover)
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- Reset + access → Rising (re-admit)
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-/
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def sieveTransition (s : SieveState) (accessCount : ℕ) (contention : ℕ) : SieveState × AccessResult :=
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match s with
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| .stable =>
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(.rising, .promote)
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| .rising =>
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if contention ≥ ContentionThreshold then
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(.unstable, .demote)
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else
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(.rising, .hit)
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| .unstable =>
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if contention ≥ ContentionThreshold then
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(.reset, .demote)
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else
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(.rising, .promote)
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| .reset =>
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(.rising, .promote)
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/-- Check if a cache line should be admitted (admission control).
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A line is admitted if:
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- There's capacity available, OR
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- An existing line can be evicted (in Reset state) -/
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def shouldAdmit (sieve : CacheSieve) (addr : ℕ) : Bool :=
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let existing := sieve.lines.filter (fun l => l.addr == addr)
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if !existing.isEmpty then
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-- Line exists: check if it's in Reset (re-admit) or Stable/Rising (keep)
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match existing.head!.state with
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| .reset => true
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| _ => true -- already admitted
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else
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-- New line: admit if capacity available or can evict
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let activeLines := sieve.lines.filter (fun l => l.state ≠ .reset)
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activeLines.length < sieve.capacity
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/-- Evict a line to make room (victim selection: oldest Unstable or Reset). -/
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def evictVictim (sieve : CacheSieve) : Option ℕ :=
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-- Prefer evicting Reset lines, then Unstable
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let resetLines := sieve.lines.filterMap (fun l =>
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if l.state == .reset then some l.addr else none)
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match resetLines.head? with
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| some addr => some addr
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| none =>
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let unstableLines := sieve.lines.filterMap (fun l =>
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if l.state == .unstable then some l.addr else none)
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unstableLines.head?
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-- ── Theorems ──────────────────────────────────────────────────────────
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/-- A stable line with an access transitions to Rising (promotion). -/
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theorem stable_access_promotes :
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sieveTransition .stable 0 0 = (.rising, .promote) := rfl
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/-- A rising line with low contention stays Rising (hit). -/
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theorem rising_low_contention_hits :
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sieveTransition .rising 5 0 = (.rising, .hit) := by
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simp [sieveTransition, ContentionThreshold]
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omega
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/-- A rising line with high contention transitions to Unstable (demote). -/
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theorem rising_high_contention_demotes :
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sieveTransition .rising 5 65536 = (.unstable, .demote) := by
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simp [sieveTransition, ContentionThreshold]
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omega
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/-- An unstable line with persistent contention transitions to Reset (evict). -/
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theorem unstable_high_contention_resets :
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sieveTransition .unstable 10 65536 = (.reset, .demote) := by
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simp [sieveTransition, ContentionThreshold]
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omega
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/-- A reset line with re-access transitions to Rising (re-admission). -/
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theorem reset_access_readmits :
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sieveTransition .reset 0 0 = (.rising, .promote) := rfl
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/-- Admission control: line is admitted when capacity is available. -/
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theorem admit_when_capacity (sieve : CacheSieve)
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(hcap : (sieve.lines.filter (fun l => l.state ≠ .reset)).length < sieve.capacity)
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(addr : ℕ) (hnew : ∀ l ∈ sieve.lines, l.addr ≠ addr) :
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shouldAdmit sieve addr = true := by
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simp [shouldAdmit]
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intro h
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exfalso
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apply hnew
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exact (List.filter_mem_cons h).head
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simp at h
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/-- Eviction prefers Reset lines over Unstable. -/
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theorem evict_prefers_reset (sieve : CacheSieve)
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(hreset : ∃ l ∈ sieve.lines, l.state == .reset) :
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evictVictim sieve = some hreset.choose := by
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simp [evictVictim]
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-- The first Reset line in the list is chosen
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sorry
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/-- COUCH gate connection: unstable→reset transition is the COUCH filter.
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When contention exceeds threshold (COUCH fails), the sieve evicts
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the line. This is the cache-level implementation of the COUCH gate
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from GCCL.lean. -/
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theorem couch_evicts_on_contention :
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∀ (accessCount : ℕ),
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sieveTransition .unstable accessCount 65536 = (.reset, .demote) := by
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intro accessCount
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simp [sieveTransition, ContentionThreshold]
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omega
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end SilverSight.CacheSieve
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