SilverSight/formal/SilverSight/CacheSieve.lean
openresearch 40e223fdd9 feat(formal): HCMR suite — 5 clean rewrites for SilverSight
Five new formal modules, all clean rewrites (not ports from Research
Stack). Based on the chiral CRT multiplexing framework.

1. HCMR.lean (Hardware Contention Markov Representation)
   - Self-loop probs: SUBLEQ=0.823, AVX-512=0.885, ring=0.0
   - Throughput = base_rate × (1 - self_loop_prob)
   - Theorems: ring > SUBLEQ > AVX-512 ordering, COUCH stability
   - Connection: self_loop = Sidon collision rate

2. CacheSieve.lean (L0 Local Sorter Cache Admission)
   - 4-state machine: Stable → Rising → Unstable → Reset
   - Admission control + victim selection
   - Theorems: stable→promote, high contention→demote, COUCH evicts
   - Connection: COUCH gate = contention threshold filter

3. Blitter6502OISC.lean (6502 OISC Blitter)
   - SUBLEQ instruction semantics: M[b] := M[b] - M[a]
   - Blitter: 3 SUBLEQ per byte (negation trick)
   - Theorems: subtract semantics, branch on ≤0, ring faster than SUBLEQ
   - Connection: blitter is the 'word SUBLEQ' regime from HCMR

4. YangMillsPerformance.lean (Distributed Performance)
   - 5 layers: cache → memory → sync → compression → network
   - Composed throughput = base × ∏(1 - overhead_i)
   - Theorems: cache highest overhead, more layers = less throughput
   - Connection: cache overhead = HCMR SUBLEQ self-loop

5. WorkloadTestbench.lean (Virtual GPU Workload Simulation)
   - 5 workload types: stream, strided, random, gather, scatter
   - Maps workloads to HCMR ops and CacheSieve states
   - Theorems: stream highest throughput, random causes Reset
   - Connection: stream = ring dispatch, random = AVX-512

Suite composition:
  WorkloadTestbench (workload → op type)
  → HCMR (op → self-loop → throughput)
  → CacheSieve (contention → admit/evict)
  → Blitter6502OISC (concrete SUBLEQ execution)
  → YangMillsPerformance (distributed stack composition)

All modules registered in lakefile.lean as SilverSightRRC roots.
Lean v4.30.0-rc2, Mathlib dependency.

Known sorries: 2 (CacheSieve.evict_prefers_reset needs List API work,
YangMillsPerformance.compression_overhead_bounded needs conservation law
formalization). All other theorems are complete.
2026-07-04 19:53:20 +00:00

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/-
CacheSieve.lean — L0 Local Sorter Cache Admission Control
Static cache filtering: decides which cache lines to admit based on
a 4-state machine. Pairs with HCMR for the complete cache performance
model (admission + contention).
Clean rewrite for SilverSight — not a port from Research Stack.
Based on the chiral CRT multiplexing framework.
States:
- Stable: line is cached, low access frequency, keep
- Rising: line is being promoted (frequency increasing)
- Unstable: line is hot but contended (may thrash)
- Reset: line evicted, must re-fetch
Admission policy:
- Stable → Rising on access
- Rising → Unstable if contention detected (HCMR self-loop high)
- Unstable → Reset if contention persists (COUCH gate fails)
- Reset → Rising on re-access (re-admission)
Connection to CRT multiplexer:
- CacheSieve decides WHICH channels to admit (admission control)
- HCMR models CONTENTION on admitted channels (throughput)
- Together: complete cache performance model
-/
import Mathlib.Data.Real.Basic
import Mathlib.Tactic
namespace SilverSight.CacheSieve
/-- Sieve state: the 4-state machine for cache admission. -/
inductive SieveState where
| stable : SieveState -- cached, low frequency, keep
| rising : SieveState -- being promoted (frequency increasing)
| unstable : SieveState -- hot but contended (may thrash)
| reset : SieveState -- evicted, must re-fetch
deriving Repr, DecidableEq
/-- Cache line with sieve state and access count. -/
structure CacheLine where
addr : -- cache line address
state : SieveState
accessCount : -- number of accesses since admission
deriving Repr
/-- The sieve: a collection of cache lines with a capacity. -/
structure CacheSieve where
lines : List CacheLine
capacity : -- max lines the cache can hold
deriving Repr
/-- Access outcome: did the access hit, miss, or promote/demote? -/
inductive AccessResult where
| hit : AccessResult -- line was stable/rising, access succeeded
| miss : AccessResult -- line was reset/absent, must fetch
| promote : AccessResult -- line promoted (stable→rising or reset→rising)
| demote : AccessResult -- line demoted (rising→unstable or unstable→reset)
deriving Repr
/-- Contention level from HCMR (self-loop probability as Q16_16 raw). -/
-- 0 = no contention, 65536 = fully contended
def ContentionThreshold : := 49152 -- 0.75 × 65536 — high contention cutoff
/-- Transition: given current state, access count, and contention, what's next?
- Stable + access → Rising (promote)
- Rising + low contention → Rising (stay, accumulating heat)
- Rising + high contention → Unstable (demote)
- Unstable + high contention → Reset (evict)
- Unstable + low contention → Rising (recover)
- Reset + access → Rising (re-admit)
-/
def sieveTransition (s : SieveState) (accessCount : ) (contention : ) : SieveState × AccessResult :=
match s with
| .stable =>
(.rising, .promote)
| .rising =>
if contention ≥ ContentionThreshold then
(.unstable, .demote)
else
(.rising, .hit)
| .unstable =>
if contention ≥ ContentionThreshold then
(.reset, .demote)
else
(.rising, .promote)
| .reset =>
(.rising, .promote)
/-- Check if a cache line should be admitted (admission control).
A line is admitted if:
- There's capacity available, OR
- An existing line can be evicted (in Reset state) -/
def shouldAdmit (sieve : CacheSieve) (addr : ) : Bool :=
let existing := sieve.lines.filter (fun l => l.addr == addr)
if !existing.isEmpty then
-- Line exists: check if it's in Reset (re-admit) or Stable/Rising (keep)
match existing.head!.state with
| .reset => true
| _ => true -- already admitted
else
-- New line: admit if capacity available or can evict
let activeLines := sieve.lines.filter (fun l => l.state ≠ .reset)
activeLines.length < sieve.capacity
/-- Evict a line to make room (victim selection: oldest Unstable or Reset). -/
def evictVictim (sieve : CacheSieve) : Option :=
-- Prefer evicting Reset lines, then Unstable
let resetLines := sieve.lines.filterMap (fun l =>
if l.state == .reset then some l.addr else none)
match resetLines.head? with
| some addr => some addr
| none =>
let unstableLines := sieve.lines.filterMap (fun l =>
if l.state == .unstable then some l.addr else none)
unstableLines.head?
-- ── Theorems ──────────────────────────────────────────────────────────
/-- A stable line with an access transitions to Rising (promotion). -/
theorem stable_access_promotes :
sieveTransition .stable 0 0 = (.rising, .promote) := rfl
/-- A rising line with low contention stays Rising (hit). -/
theorem rising_low_contention_hits :
sieveTransition .rising 5 0 = (.rising, .hit) := by
simp [sieveTransition, ContentionThreshold]
omega
/-- A rising line with high contention transitions to Unstable (demote). -/
theorem rising_high_contention_demotes :
sieveTransition .rising 5 65536 = (.unstable, .demote) := by
simp [sieveTransition, ContentionThreshold]
omega
/-- An unstable line with persistent contention transitions to Reset (evict). -/
theorem unstable_high_contention_resets :
sieveTransition .unstable 10 65536 = (.reset, .demote) := by
simp [sieveTransition, ContentionThreshold]
omega
/-- A reset line with re-access transitions to Rising (re-admission). -/
theorem reset_access_readmits :
sieveTransition .reset 0 0 = (.rising, .promote) := rfl
/-- Admission control: line is admitted when capacity is available. -/
theorem admit_when_capacity (sieve : CacheSieve)
(hcap : (sieve.lines.filter (fun l => l.state ≠ .reset)).length < sieve.capacity)
(addr : ) (hnew : ∀ l ∈ sieve.lines, l.addr ≠ addr) :
shouldAdmit sieve addr = true := by
simp [shouldAdmit]
intro h
exfalso
apply hnew
exact (List.filter_mem_cons h).head
simp at h
/-- Eviction prefers Reset lines over Unstable. -/
theorem evict_prefers_reset (sieve : CacheSieve)
(hreset : ∃ l ∈ sieve.lines, l.state == .reset) :
evictVictim sieve = some hreset.choose := by
simp [evictVictim]
-- The first Reset line in the list is chosen
sorry
/-- COUCH gate connection: unstable→reset transition is the COUCH filter.
When contention exceeds threshold (COUCH fails), the sieve evicts
the line. This is the cache-level implementation of the COUCH gate
from GCCL.lean. -/
theorem couch_evicts_on_contention :
∀ (accessCount : ),
sieveTransition .unstable accessCount 65536 = (.reset, .demote) := by
intro accessCount
simp [sieveTransition, ContentionThreshold]
omega
end SilverSight.CacheSieve