mirror of
https://github.com/allaunthefox/SilverSight.git
synced 2026-07-31 01:25:21 +00:00
Julia port: - Extended type tracking from Bool (is_q16) to Int8 tri-state (TYPE_BOOL/Q16/Q0) - Added ADD_SAT_Q0 / SUB_SAT_Q0 primitive handling - Added avm_q0_clamp for symmetric Q0_16 range [-32767, 32767] R port: - Added PRIM_ADD_Q0 / PRIM_SUB_Q0 primitives - Added push_q0 instruction, make_q0 / is_q0 helpers - Added avm_q0_clamp for symmetric Q0_16 range - Fixed LOAD to preserve type tag on restore All three ports now support the full AVM ISA type universe (Q0_16, Q16_16, Bool). |
||
|---|---|---|
| .. | ||
| AVMIsa | ||
| CoreFormalism | ||
| nuvmap | ||
| README.md | ||
SilverSight — Language Port
Source of truth: /home/allaun/SilverSight/formal/ (Lean 4)
This directory mirrors the Lean module structure. Each file implements the same theorems/algorithms in this language, providing independent cross-validation across runtimes.
Module map: CoreFormalism/ → formal/CoreFormalism/ (braid, Q16_16, Sidon) SilverSight/ → formal/SilverSight/ (PIST, AVMIsa, RRC) BindingSite/ → formal/BindingSite/ (DNA, hachimoji) PVGS_DQ_Bridge/ → formal/PVGS_DQ_Bridge/ UniversalEncoding/ → formal/UniversalEncoding/ nuvmap/ → python/nuvmap/ (NUVMAP projection)