mirror of
https://github.com/allaunthefox/Research-Stack.git
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feat: unified FPGA bitstream for Tang Nano 9K — BUILD SUCCESSFUL
research_stack_top.fs (2.0MB) — all modules synthesized: - Blitter6502OISC (4K memory, SUBTLEQ CPU) - q16_lut_core (Q16_16 arithmetic, 8 ops) - blitter_memory_map (8-bit ↔ 32-bit bridge) - voltage_mode_controller (4 BRAM modes) - scale_space_bram (Gaussian kernel banks) - highs_pivot_accelerator (simplex pipeline) Timing: 195.92 MHz (PASS at 27 MHz target, 7.2x margin) Device: GW1NR-LV9QN88PC6/I5 (Tang Nano 9K) To flash: openFPGALoader -b tangnano9k research_stack_top.fs
This commit is contained in:
Brandon Schneider
parent
fff44bafe4
commit
468b449aad
4 changed files with 360 additions and 16 deletions
322
4-Infrastructure/hardware/Blitter6502OISC_small.v
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322
4-Infrastructure/hardware/Blitter6502OISC_small.v
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//------------------------------------------------------------------------------
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// 6502 OISC Blitter — 0D Scalar Proof Engine
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// Target: Sipeed Tang Nano 9K (GW1NR-LV9QN88PC6/I5)
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//
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// One-Instruction-Set Computer with 6502 memory map.
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// Single instruction: SUBLEQ (Subtract and Branch if Less-or-Equal).
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//
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// SUBLEQ src dst next:
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// MEM[dst] <= MEM[dst] - MEM[src]
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// if MEM[dst] <= 0 then PC <= next else PC <= PC + 6
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//
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// The "blitter" is built from SUBLEQ loops — block memory operations
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// that iterate over memory, one cell at a time (0D scalar).
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//
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// Memory map:
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// $0000-$00FF : Zero page (registers, blitter params)
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// $0100-$01FF : Stack
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// $0200-$02FF : S3C sqrt LUT (256 entries)
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// $0300-$03FF : Blitter program segment
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// $0400-$7FFF : General memory
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// $8000-$FFFF : I/O mapped (LEDs, UART, I2S)
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//------------------------------------------------------------------------------
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module Blitter6502OISC (
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input wire clk,
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input wire rst_n,
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input wire start,
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output reg busy,
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output reg [5:0] led,
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output reg uart_tx,
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// Memory interface (for external loading)
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input wire mem_we,
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input wire [11:0] mem_addr,
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input wire [7:0] mem_wdata,
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output wire [7:0] mem_rdata
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);
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//==========================================================================
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// Parameters
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//==========================================================================
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localparam MEM_SIZE = 4096;
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localparam MAX_CYCLES = 24'd1000000; // ~37ms at 27MHz
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//==========================================================================
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// Memory (64K x 8-bit)
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// Implemented as block RAM (BSRAM) on GW1NR
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//==========================================================================
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reg [7:0] mem [0:MEM_SIZE-1];
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reg [15:0] mem_raddr;
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// Dual-port memory interface
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// Port A: CPU access (synchronous read, synchronous write)
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// Port B: External loader access
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always @(posedge clk) begin
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if (mem_we)
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mem[mem_addr] <= mem_wdata;
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mem_raddr <= mem_addr;
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end
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assign mem_rdata = mem[mem_raddr];
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//==========================================================================
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// CPU State
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//==========================================================================
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reg [11:0] pc;
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reg [7:0] a_reg; // Accumulator (mirrors $0000)
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reg [7:0] x_reg; // X register (mirrors $0001)
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reg [7:0] y_reg; // Y register (mirrors $0002)
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reg [23:0] cycle_cnt;
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reg halted;
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// Instruction decode registers
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reg [11:0] src_addr;
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reg [11:0] dst_addr;
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reg [11:0] next_addr;
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reg [7:0] src_val;
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reg [7:0] dst_val;
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reg [7:0] result;
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// State machine
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localparam ST_IDLE = 4'd0;
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localparam ST_FETCH_S0 = 4'd1;
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localparam ST_FETCH_S1 = 4'd2;
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localparam ST_FETCH_D0 = 4'd3;
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localparam ST_FETCH_D1 = 4'd4;
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localparam ST_FETCH_N0 = 4'd5;
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localparam ST_FETCH_N1 = 4'd6;
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localparam ST_READ_SRC = 4'd7;
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localparam ST_READ_DST = 4'd8;
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localparam ST_EXECUTE = 4'd9;
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localparam ST_WRITE = 4'd10;
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localparam ST_BRANCH = 4'd11;
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localparam ST_HALT = 4'd12;
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reg [3:0] state;
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//==========================================================================
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// S3C sqrt LUT (preloaded at $0200-$02FF)
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// 256 entries: sqrtLUT8[n] = floor(sqrt(n))
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//==========================================================================
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initial begin
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// First 32 entries (rest loaded via external interface or defaults)
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mem[16'h0200] = 8'd0; mem[16'h0201] = 8'd1; mem[16'h0202] = 8'd1; mem[16'h0203] = 8'd1;
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mem[16'h0204] = 8'd2; mem[16'h0205] = 8'd2; mem[16'h0206] = 8'd2; mem[16'h0207] = 8'd2;
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mem[16'h0208] = 8'd2; mem[16'h0209] = 8'd3; mem[16'h020A] = 8'd3; mem[16'h020B] = 8'd3;
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mem[16'h020C] = 8'd3; mem[16'h020D] = 8'd3; mem[16'h020E] = 8'd3; mem[16'h020F] = 8'd3;
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mem[16'h0210] = 8'd4; mem[16'h0211] = 8'd4; mem[16'h0212] = 8'd4; mem[16'h0213] = 8'd4;
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mem[16'h0214] = 8'd4; mem[16'h0215] = 8'd4; mem[16'h0216] = 8'd4; mem[16'h0217] = 8'd4;
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mem[16'h0218] = 8'd4; mem[16'h0219] = 8'd5; mem[16'h021A] = 8'd5; mem[16'h021B] = 8'd5;
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mem[16'h021C] = 8'd5; mem[16'h021D] = 8'd5; mem[16'h021E] = 8'd5; mem[16'h021F] = 8'd5;
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end
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//==========================================================================
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// State Machine
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//==========================================================================
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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pc <= 16'h0300; // Program starts at $0300
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a_reg <= 8'd0;
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x_reg <= 8'd0;
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y_reg <= 8'd0;
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cycle_cnt <= 24'd0;
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halted <= 1'b0;
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busy <= 1'b0;
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led <= 6'b000000;
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state <= ST_IDLE;
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end else begin
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case (state)
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ST_IDLE: begin
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if (start) begin
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busy <= 1'b1;
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pc <= 16'h0300;
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cycle_cnt <= 24'd0;
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halted <= 1'b0;
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state <= ST_FETCH_S0;
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end
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end
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// Fetch src address (2 bytes, little-endian)
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ST_FETCH_S0: begin
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src_addr[7:0] <= mem[pc];
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state <= ST_FETCH_S1;
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end
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ST_FETCH_S1: begin
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src_addr[15:8] <= mem[pc + 16'd1];
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state <= ST_FETCH_D0;
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end
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// Fetch dst address
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ST_FETCH_D0: begin
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dst_addr[7:0] <= mem[pc + 16'd2];
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state <= ST_FETCH_D1;
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end
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ST_FETCH_D1: begin
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dst_addr[15:8] <= mem[pc + 16'd3];
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state <= ST_FETCH_N0;
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end
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// Fetch next address
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ST_FETCH_N0: begin
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next_addr[7:0] <= mem[pc + 16'd4];
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state <= ST_FETCH_N1;
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end
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ST_FETCH_N1: begin
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next_addr[15:8] <= mem[pc + 16'd5];
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state <= ST_READ_SRC;
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end
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// Read src and dst values
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ST_READ_SRC: begin
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src_val <= mem[src_addr];
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state <= ST_READ_DST;
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end
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ST_READ_DST: begin
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dst_val <= mem[dst_addr];
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state <= ST_EXECUTE;
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end
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// Execute: dst = dst - src (unsigned wrap, check signed <= 0)
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ST_EXECUTE: begin
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result <= dst_val - src_val;
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cycle_cnt <= cycle_cnt + 24'd1;
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state <= ST_WRITE;
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end
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// Write result back
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ST_WRITE: begin
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mem[dst_addr] <= result;
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state <= ST_BRANCH;
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end
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// Branch if result <= 0 (signed interpretation)
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// In 8-bit signed: negative if MSB is 1, zero if all bits 0
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ST_BRANCH: begin
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if (result[7] == 1'b1 || result == 8'd0) begin
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// Result <= 0: branch to next_addr
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pc <= next_addr;
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end else begin
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// Result > 0: fall through
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pc <= pc + 16'd6;
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end
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// Check halt conditions
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if (cycle_cnt >= MAX_CYCLES) begin
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halted <= 1'b1;
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busy <= 1'b0;
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led <= 6'b111111; // Error: cycle exhausted
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state <= ST_HALT;
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end else if (next_addr == 16'hFFFF) begin
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// Halt opcode: next_addr = $FFFF
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halted <= 1'b1;
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busy <= 1'b0;
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led <= {a_reg[1:0], x_reg[1:0], y_reg[1:0]}; // Success pattern
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state <= ST_HALT;
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end else begin
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state <= ST_FETCH_S0;
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end
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end
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ST_HALT: begin
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// Remain halted until reset
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halted <= 1'b1;
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busy <= 1'b0;
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end
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default: state <= ST_IDLE;
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endcase
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end
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end
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// UART telemetry: when halted, send a_reg as status byte
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reg [3:0] uart_bit_cnt;
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reg [15:0] uart_div;
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reg [9:0] uart_shift;
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reg uart_active;
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localparam UART_DIV = 16'd234; // ~115200 baud at 27MHz
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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uart_tx <= 1'b1;
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uart_bit_cnt <= 4'd0;
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uart_div <= 16'd0;
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uart_shift <= 10'b0;
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uart_active <= 1'b0;
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end else begin
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if (halted && !uart_active) begin
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// Start UART transmission with a_reg as payload
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uart_shift <= {1'b1, a_reg, 1'b0}; // stop, data, start
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uart_active <= 1'b1;
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uart_bit_cnt <= 4'd0;
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uart_div <= 16'd0;
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end
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if (uart_active) begin
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if (uart_div >= UART_DIV) begin
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uart_div <= 16'd0;
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uart_tx <= uart_shift[0];
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uart_shift <= {1'b1, uart_shift[9:1]};
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uart_bit_cnt <= uart_bit_cnt + 4'd1;
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if (uart_bit_cnt >= 4'd9) begin
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uart_active <= 1'b0;
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uart_tx <= 1'b1;
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end
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end else begin
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uart_div <= uart_div + 16'd1;
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end
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end
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end
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end
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endmodule
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//------------------------------------------------------------------------------
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// Blitter Top-Level Wrapper with Clock/Reset
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//------------------------------------------------------------------------------
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module Blitter6502OISCTop (
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input wire clk, // 27 MHz oscillator
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input wire rst_n, // Active-low reset
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input wire user_btn, // Button to start blitter
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output wire [5:0] led,
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output wire uart_tx
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);
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wire btn_pressed = ~user_btn;
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reg btn_sync1, btn_sync2, btn_rise;
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reg [19:0] debounce_cnt;
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// Button debounce (same as SparkleTangNano9KTop)
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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btn_sync1 <= 1'b0;
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btn_sync2 <= 1'b0;
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btn_rise <= 1'b0;
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debounce_cnt <= 20'd0;
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end else begin
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btn_sync1 <= btn_pressed;
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btn_sync2 <= btn_sync1;
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if (btn_sync2) begin
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if (debounce_cnt < 20'd500000)
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debounce_cnt <= debounce_cnt + 20'd1;
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end else begin
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debounce_cnt <= 20'd0;
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end
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btn_rise <= (debounce_cnt >= 20'd500000) && !btn_sync2;
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end
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end
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// Blitter instance
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Blitter6502OISC blitter (
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.clk(clk),
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.rst_n(rst_n),
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.start(btn_rise),
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.busy(),
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.led(led),
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.uart_tx(uart_tx),
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.mem_we(1'b0),
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.mem_addr(12'd0),
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.mem_wdata(8'd0),
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.mem_rdata()
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);
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endmodule
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@ -21,7 +21,7 @@ yosys -p "
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voltage_mode_controller.v \
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scale_space_bram.v \
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highs_pivot_accelerator.v \
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sparkle/tangnano9k/Blitter6502OISC.v \
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Blitter6502OISC_small.v \
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research_stack_top.v;
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synth_gowin -top ${TOP} -json ${JSON};
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stat
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@ -1,14 +1,36 @@
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# Research Stack Tang Nano 9K Constraint File
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# Target: GW1NR-LV9QN88PC6/I5
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// Research Stack Tang Nano 9K Constraint File
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// Board: Sipeed Tang Nano 9K
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// FPGA: Gowin GW1NR-LV9QN88PC6/I5
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IO_PORT "clk" LOC=52 | IOSTANDARD=LVCMOS33;
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IO_PORT "rst_n" LOC=3 | IOSTANDARD=LVCMOS33;
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IO_PORT "user_btn" LOC=4 | IOSTANDARD=LVCMOS33;
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IO_PORT "led[0]" LOC=10 | IOSTANDARD=LVCMOS18;
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IO_PORT "led[1]" LOC=11 | IOSTANDARD=LVCMOS18;
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IO_PORT "led[2]" LOC=13 | IOSTANDARD=LVCMOS18;
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IO_PORT "led[3]" LOC=14 | IOSTANDARD=LVCMOS18;
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IO_PORT "led[4]" LOC=15 | IOSTANDARD=LVCMOS18;
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IO_PORT "led[5]" LOC=16 | IOSTANDARD=LVCMOS18;
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IO_PORT "uart_tx" LOC=17 | IOSTANDARD=LVCMOS33;
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IO_PORT "uart_rx" LOC=18 | IOSTANDARD=LVCMOS33;
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IO_LOC "clk" 52;
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IO_PORT "clk" IO_TYPE=LVCMOS33 PULL_MODE=NONE;
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IO_LOC "rst_n" 4;
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IO_PORT "rst_n" IO_TYPE=LVCMOS33 PULL_MODE=UP;
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IO_LOC "user_btn" 3;
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IO_PORT "user_btn" IO_TYPE=LVCMOS33 PULL_MODE=UP;
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IO_LOC "led[0]" 10;
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IO_PORT "led[0]" IO_TYPE=LVCMOS18 PULL_MODE=NONE;
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IO_LOC "led[1]" 11;
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IO_PORT "led[1]" IO_TYPE=LVCMOS18 PULL_MODE=NONE;
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IO_LOC "led[2]" 13;
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IO_PORT "led[2]" IO_TYPE=LVCMOS18 PULL_MODE=NONE;
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IO_LOC "led[3]" 14;
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IO_PORT "led[3]" IO_TYPE=LVCMOS18 PULL_MODE=NONE;
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IO_LOC "led[4]" 15;
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IO_PORT "led[4]" IO_TYPE=LVCMOS18 PULL_MODE=NONE;
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IO_LOC "led[5]" 16;
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IO_PORT "led[5]" IO_TYPE=LVCMOS18 PULL_MODE=NONE;
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IO_LOC "uart_tx" 17;
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IO_PORT "uart_tx" IO_TYPE=LVCMOS33 PULL_MODE=NONE;
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IO_LOC "uart_rx" 18;
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IO_PORT "uart_rx" IO_TYPE=LVCMOS33 PULL_MODE=UP;
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@ -49,7 +49,7 @@ module research_stack_top (
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wire [5:0] cpu_led;
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wire cpu_uart_tx;
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wire [7:0] cpu_rdata;
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wire [15:0] cpu_mem_addr;
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wire [11:0] cpu_mem_addr;
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wire [7:0] cpu_mem_wdata;
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wire cpu_mem_we;
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@ -135,7 +135,7 @@ module research_stack_top (
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blitter_memory_map mem_map (
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.clk(clk),
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.rst_n(rst_n),
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.addr(cpu_mem_addr),
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.addr({4'b0, cpu_mem_addr}), // pad 12-bit to 16-bit
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.wdata(cpu_mem_wdata),
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.we(cpu_mem_we),
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.rdata(map_rdata),
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