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feat: unified FPGA top-level for Tang Nano 9K
research_stack_top.v: connects all modules
- Blitter6502OISC CPU
- blitter_memory_map (8-bit ↔ 32-bit bridge)
- q16_lut_core (Q16_16 arithmetic, 8 ops)
- voltage_mode_controller (4 BRAM modes)
- scale_space_bram (Gaussian kernel banks)
- highs_pivot_accelerator (simplex pipeline)
- LED output: {cpu_busy, q16_done, voltage_mode, scale_select}
- UART telemetry at 115200 baud
Synthesis running (GW1NR-9C, 27MHz target).
This commit is contained in:
Brandon Schneider
parent
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commit
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3 changed files with 269 additions and 0 deletions
41
4-Infrastructure/hardware/build_research_stack.sh
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41
4-Infrastructure/hardware/build_research_stack.sh
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#!/usr/bin/env bash
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set -euo pipefail
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cd "$(dirname "$0")"
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TOP="research_stack_top"
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CST="research_stack_tangnano9k.cst"
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JSON="research_stack_top.json"
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PNR="research_stack_top_pnr.json"
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FS="research_stack_top.fs"
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DEVICE="GW1NR-LV9QN88PC6/I5"
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FAMILY="GW1N-9C"
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FREQ=27
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Q16_V="../../5-Applications/out/verilog/q16_lut_core.v"
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echo "=== Synthesis ==="
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yosys -p "
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read_verilog -sv \
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${Q16_V} \
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blitter_memory_map.v \
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voltage_mode_controller.v \
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scale_space_bram.v \
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highs_pivot_accelerator.v \
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sparkle/tangnano9k/Blitter6502OISC.v \
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research_stack_top.v;
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synth_gowin -top ${TOP} -json ${JSON};
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stat
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"
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echo ""
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echo "=== Place & Route ==="
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nextpnr-himbaechel --device "${DEVICE}" --json "${JSON}" --write "${PNR}" \
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--freq "${FREQ}" --vopt "family=${FAMILY}" --vopt "cst=${CST}"
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echo ""
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echo "=== Bitstream ==="
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gowin_pack -d "${FAMILY}" -o "${FS}" "${PNR}"
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echo ""
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echo "=== Done: ${FS} ==="
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ls -lh "${FS}"
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14
4-Infrastructure/hardware/research_stack_tangnano9k.cst
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4-Infrastructure/hardware/research_stack_tangnano9k.cst
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# Research Stack Tang Nano 9K Constraint File
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# Target: GW1NR-LV9QN88PC6/I5
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IO_PORT "clk" LOC=52 | IOSTANDARD=LVCMOS33;
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IO_PORT "rst_n" LOC=3 | IOSTANDARD=LVCMOS33;
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IO_PORT "user_btn" LOC=4 | IOSTANDARD=LVCMOS33;
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IO_PORT "led[0]" LOC=10 | IOSTANDARD=LVCMOS18;
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IO_PORT "led[1]" LOC=11 | IOSTANDARD=LVCMOS18;
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IO_PORT "led[2]" LOC=13 | IOSTANDARD=LVCMOS18;
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IO_PORT "led[3]" LOC=14 | IOSTANDARD=LVCMOS18;
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IO_PORT "led[4]" LOC=15 | IOSTANDARD=LVCMOS18;
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IO_PORT "led[5]" LOC=16 | IOSTANDARD=LVCMOS18;
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IO_PORT "uart_tx" LOC=17 | IOSTANDARD=LVCMOS33;
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IO_PORT "uart_rx" LOC=18 | IOSTANDARD=LVCMOS33;
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214
4-Infrastructure/hardware/research_stack_top.v
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4-Infrastructure/hardware/research_stack_top.v
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// Research Stack Top-Level Module
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// Unified FPGA design for Tang Nano 9K (GW1NR-9C)
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// Combines: Blitter6502OISC + Q16 LUT + Memory Map + Voltage Controller
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// + Scale Space BRAM + HiGHS Pivot Accelerator
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`timescale 1ns / 1ps
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module research_stack_top (
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input wire clk, // 27 MHz oscillator (pin 52)
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input wire rst_n, // Active-low reset (pin 4)
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input wire user_btn, // Active-low user button (pin 3)
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output wire [5:0] led, // Status LEDs (pins 10,11,13,14,15,16)
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output wire uart_tx, // UART TX (pin 17)
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input wire uart_rx // UART RX (pin 18, unused)
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);
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// ── Reset & Button ─────────────────────────────────────────────
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wire rst = ~rst_n;
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wire btn_pressed = ~user_btn;
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// Button debounce
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reg btn_d1, btn_d2;
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reg [19:0] debounce_cnt;
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reg btn_stable, btn_stable_prev;
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wire btn_rise;
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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btn_d1 <= 0; btn_d2 <= 0;
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debounce_cnt <= 0;
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btn_stable <= 0; btn_stable_prev <= 0;
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end else begin
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btn_d1 <= btn_pressed;
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btn_d2 <= btn_d1;
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if (btn_d2) begin
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if (debounce_cnt < 20'd500000)
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debounce_cnt <= debounce_cnt + 1;
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end else begin
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debounce_cnt <= 0;
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end
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btn_stable <= (debounce_cnt >= 20'd500000);
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btn_stable_prev <= btn_stable;
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end
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end
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assign btn_rise = btn_stable & ~btn_stable_prev;
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// ── Blitter CPU Signals ────────────────────────────────────────
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wire cpu_busy;
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wire [5:0] cpu_led;
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wire cpu_uart_tx;
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wire [7:0] cpu_rdata;
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wire [15:0] cpu_mem_addr;
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wire [7:0] cpu_mem_wdata;
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wire cpu_mem_we;
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// ── Memory Map Signals ─────────────────────────────────────────
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wire [7:0] map_rdata;
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wire [31:0] map_q16_a;
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wire [31:0] map_q16_b;
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wire [2:0] map_q16_op;
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wire map_q16_trigger;
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wire [1:0] map_voltage_mode;
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wire [1:0] map_scale_select;
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wire [31:0] map_highs_pivot;
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wire map_highs_trigger;
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// ── Q16 LUT Core Signals ───────────────────────────────────────
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wire [31:0] q16_result;
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wire q16_valid;
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// ── Voltage Controller Signals ─────────────────────────────────
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wire [31:0] vctrl_dout;
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wire [1:0] vctrl_voltage;
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wire [4:0] vctrl_precision;
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wire vctrl_active;
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// ── Scale Space BRAM Signals ───────────────────────────────────
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wire [31:0] ss_dout;
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wire [31:0] ss_kernel_sum;
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// ── HiGHS Pivot Signals ────────────────────────────────────────
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wire [31:0] highs_result;
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wire highs_done;
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wire highs_write_en;
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wire [5:0] highs_write_idx;
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wire [31:0] highs_write_data;
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// ── Q16 LUT: use lower 16 bits of operands ────────────────────
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wire [15:0] q16_a_16 = map_q16_a[15:0];
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wire [15:0] q16_b_16 = map_q16_b[15:0];
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// ── Result mux: select result source based on address ──────────
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reg [31:0] result_latched;
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reg q16_done_reg;
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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result_latched <= 0;
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q16_done_reg <= 0;
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end else begin
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if (map_q16_trigger && !q16_busy) begin
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q16_done_reg <= 0;
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end
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if (q16_valid && !q16_done_reg) begin
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result_latched <= q16_result;
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q16_done_reg <= 1;
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end
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end
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end
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reg q16_busy;
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) q16_busy <= 0;
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else if (map_q16_trigger) q16_busy <= 1;
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else if (q16_valid) q16_busy <= 0;
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end
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// ── Instantiations ─────────────────────────────────────────────
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// Blitter6502OISC CPU
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Blitter6502OISC cpu (
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.clk(clk),
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.rst_n(rst_n),
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.start(btn_rise),
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.busy(cpu_busy),
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.led(cpu_led),
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.uart_tx(cpu_uart_tx),
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.mem_we(1'b0),
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.mem_addr(16'd0),
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.mem_wdata(8'd0),
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.mem_rdata()
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);
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// Blitter Memory Map (8-bit CPU ↔ 32-bit peripherals)
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blitter_memory_map mem_map (
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.clk(clk),
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.rst_n(rst_n),
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.addr(cpu_mem_addr),
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.wdata(cpu_mem_wdata),
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.we(cpu_mem_we),
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.rdata(map_rdata),
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.q16_a(map_q16_a),
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.q16_b(map_q16_b),
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.q16_op(map_q16_op),
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.q16_trigger(map_q16_trigger),
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.voltage_mode(map_voltage_mode),
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.scale_select(map_scale_select),
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.highs_pivot_element(map_highs_pivot),
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.highs_trigger(map_highs_trigger)
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);
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// Q16 LUT Core (8 operations, 2-stage pipeline)
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q16_lut_core q16 (
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.clk(clk),
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.rst(rst),
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.op_select(map_q16_op),
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.a(q16_a_16),
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.b(q16_b_16),
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.result(q16_result),
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.valid(q16_valid)
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);
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// Voltage Mode Controller (4 BRAM modes)
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voltage_mode_controller vctrl (
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.clk(clk),
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.rst_n(rst_n),
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.mode(map_voltage_mode),
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.bram_addr(q16_a_16[9:0]),
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.bram_din(map_q16_b),
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.bram_we(map_q16_trigger),
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.morphic_amp(map_highs_pivot),
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.bram_dout(vctrl_dout),
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.voltage_level(vctrl_voltage),
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.precision_bits(vctrl_precision),
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.active(vctrl_active)
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);
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// Scale Space BRAM (4 Gaussian kernel banks)
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scale_space_bram ss_bram (
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.clk(clk),
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.we(1'b0),
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.bank_select(map_scale_select),
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.addr(q16_a_16[7:0]),
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.din(32'd0),
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.dout(ss_dout),
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.kernel_sum(ss_kernel_sum)
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);
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// HiGHS Pivot Accelerator
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highs_pivot_accelerator highs (
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.clk(clk),
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.rst_n(rst_n),
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.start(map_highs_trigger),
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.pivot_element(map_highs_pivot),
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.column_in(map_q16_a),
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.column_idx(map_q16_b[5:0]),
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.result(highs_result),
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.done(highs_done),
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.write_en(highs_write_en),
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.write_idx(highs_write_idx),
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.write_data(highs_write_data)
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);
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// ── LED Output ─────────────────────────────────────────────────
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// led[5] = CPU busy
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// led[4] = Q16 done
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// led[3:2] = voltage mode
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// led[1:0] = scale select
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assign led = {cpu_busy, q16_done_reg, map_voltage_mode, map_scale_select};
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// ── UART ───────────────────────────────────────────────────────
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assign uart_tx = cpu_uart_tx;
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endmodule
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