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https://github.com/allaunthefox/Research-Stack.git
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fff44bafe4
research_stack_top.v: connects all modules
- Blitter6502OISC CPU
- blitter_memory_map (8-bit ↔ 32-bit bridge)
- q16_lut_core (Q16_16 arithmetic, 8 ops)
- voltage_mode_controller (4 BRAM modes)
- scale_space_bram (Gaussian kernel banks)
- highs_pivot_accelerator (simplex pipeline)
- LED output: {cpu_busy, q16_done, voltage_mode, scale_select}
- UART telemetry at 115200 baud
Synthesis running (GW1NR-9C, 27MHz target).
14 lines
682 B
Text
14 lines
682 B
Text
# Research Stack Tang Nano 9K Constraint File
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# Target: GW1NR-LV9QN88PC6/I5
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IO_PORT "clk" LOC=52 | IOSTANDARD=LVCMOS33;
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IO_PORT "rst_n" LOC=3 | IOSTANDARD=LVCMOS33;
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IO_PORT "user_btn" LOC=4 | IOSTANDARD=LVCMOS33;
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IO_PORT "led[0]" LOC=10 | IOSTANDARD=LVCMOS18;
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IO_PORT "led[1]" LOC=11 | IOSTANDARD=LVCMOS18;
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IO_PORT "led[2]" LOC=13 | IOSTANDARD=LVCMOS18;
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IO_PORT "led[3]" LOC=14 | IOSTANDARD=LVCMOS18;
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IO_PORT "led[4]" LOC=15 | IOSTANDARD=LVCMOS18;
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IO_PORT "led[5]" LOC=16 | IOSTANDARD=LVCMOS18;
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IO_PORT "uart_tx" LOC=17 | IOSTANDARD=LVCMOS33;
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IO_PORT "uart_rx" LOC=18 | IOSTANDARD=LVCMOS33;
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