Brandon Schneider
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ba203ca971
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feat: spatial hash grid — GPU-style particle physics (Python + FPGA)
Ported from ScaleSpaceSynth (WebGPU particle simulator):
- 64×64×64 spatial hash, 32 particles/cell, lock-free insertion
- Curl noise: divergence-free 3D turbulence
- Pairwise forces: attractive (ratio>0.15) + repulsive (ratio<=0.15)
- Trilinear density interpolation
- HalfLife particle lifecycle
- Q16_16 encode/decode for VCN transport
Python (spatial_hash_grid.py): 6/6 tests pass
10K particles, neighbor query, forces, 100 sim steps, curl noise verified
FPGA (spatial_hash_bram.v):
16×16×16 grid, dual-port BRAM, 27-cycle neighbor scan
Density → voltage mode selector (STORE/COMPUTE/APPROX/MORPHIC)
Integrated into research_stack_top.v
Same pattern as ScaleSpaceSynth GPU:
GPU: atomicAdd for lock-free cell assignment
FPGA: BRAM read-modify-write for cell assignment
Ray: content-addressed ObjectRef for lock-free reads
All: partition space → compute density → find structure at multiple scales
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2026-05-30 01:25:19 -05:00 |
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Brandon Schneider
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9f304abab0
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feat: fractal dimension — DBC algorithm (Python + FPGA)
Paper: 'Ultra-fast computation of fractal dimension for RGB images'
(Pattern Analysis and Applications, 2025)
Python (fractal_dimension.py):
- DBC algorithm with numpy vectorization (29x faster than scalar)
- fd_compress_hint: FD → voltage mode (STORE/COMPUTE/APPROX/MORPHIC)
- 7/7 tests pass (Sierpinski, random, gradient, checkerboard, fBm, constant, RGB)
- Q16_16 integer arithmetic internally
FPGA (fractal_box_counter.v + fractal_fd_selector.v):
- 5-state FSM: IDLE → COLLECT → FINALIZE → STORE_LOG → REGRESS → DONE
- 8 power-of-two scales (2, 4, 8, ..., 256)
- Linear regression via Q16_16 64-bit arithmetic
- FD clamped to [1.0, 3.0] in Q16_16
- Selector: FD < 2.3 → STORE, < 2.6 → COMPUTE, < 2.9 → APPROX, >= 2.9 → MORPHIC
- Integrated into research_stack_top.v
FD drives adaptive compression:
Low FD (smooth) → STORE mode (minimal compression)
High FD (rough) → MORPHIC mode (aggressive compression)
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2026-05-29 20:45:21 -05:00 |
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Brandon Schneider
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09f2f3044a
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feat: unified FPGA bitstream for Tang Nano 9K — BUILD SUCCESSFUL
research_stack_top.fs (2.0MB) — all modules synthesized:
- Blitter6502OISC (4K memory, SUBTLEQ CPU)
- q16_lut_core (Q16_16 arithmetic, 8 ops)
- blitter_memory_map (8-bit ↔ 32-bit bridge)
- voltage_mode_controller (4 BRAM modes)
- scale_space_bram (Gaussian kernel banks)
- highs_pivot_accelerator (simplex pipeline)
Timing: 195.92 MHz (PASS at 27 MHz target, 7.2x margin)
Device: GW1NR-LV9QN88PC6/I5 (Tang Nano 9K)
To flash: openFPGALoader -b tangnano9k research_stack_top.fs
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2026-05-28 16:32:05 -05:00 |
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Brandon Schneider
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cd6f09d333
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feat: unified FPGA top-level for Tang Nano 9K
research_stack_top.v: connects all modules
- Blitter6502OISC CPU
- blitter_memory_map (8-bit ↔ 32-bit bridge)
- q16_lut_core (Q16_16 arithmetic, 8 ops)
- voltage_mode_controller (4 BRAM modes)
- scale_space_bram (Gaussian kernel banks)
- highs_pivot_accelerator (simplex pipeline)
- LED output: {cpu_busy, q16_done, voltage_mode, scale_select}
- UART telemetry at 115200 baud
Synthesis running (GW1NR-9C, 27MHz target).
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2026-05-28 16:16:54 -05:00 |
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