Research-Stack

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Author	SHA1	Message	Date
Brandon Schneider	270ef14e21	fix: UART bug (retransmit) + auto-start + LED heartbeat + sim verification Blitter6502OISC_small.v: - Added uart_sent flag to prevent UART retransmission - Verified via Verilator: UART sends exactly one byte on halt - Test byte: 0xAA (recognizable pattern) research_stack_top.v: - Auto-start logic (100ms after reset, no button needed) - LED shows heartbeat when CPU running, register values on halt research_stack_tangnano9k.cst: - uart_tx=17, uart_rx=18 (matches Sparkle reference design) Simulation results (Verilator): - uart_test.v: 115 bytes in 300K cycles (continuous TX verified) - research_stack_top: UART fires after Blitter halt, 0xAA byte sent - LED pattern changes from IDLE to RUNNING to HALTED	2026-05-28 21:42:11 -05:00
Brandon Schneider	6a9fcdd115	fix: Blitter UART divisor 234→233 to match Lean uartBaudDivisor proof Both now 115384 baud at 27MHz (within 0.16% of 115200). Lean theorem uartBaudRateHz_within_1pct_of_115200 applies to both.	2026-05-28 16:36:37 -05:00
Brandon Schneider	468b449aad	feat: unified FPGA bitstream for Tang Nano 9K — BUILD SUCCESSFUL research_stack_top.fs (2.0MB) — all modules synthesized: - Blitter6502OISC (4K memory, SUBTLEQ CPU) - q16_lut_core (Q16_16 arithmetic, 8 ops) - blitter_memory_map (8-bit ↔ 32-bit bridge) - voltage_mode_controller (4 BRAM modes) - scale_space_bram (Gaussian kernel banks) - highs_pivot_accelerator (simplex pipeline) Timing: 195.92 MHz (PASS at 27 MHz target, 7.2x margin) Device: GW1NR-LV9QN88PC6/I5 (Tang Nano 9K) To flash: openFPGALoader -b tangnano9k research_stack_top.fs	2026-05-28 16:32:05 -05:00

Author

SHA1

Message

Date

Brandon Schneider

270ef14e21

fix: UART bug (retransmit) + auto-start + LED heartbeat + sim verification

Blitter6502OISC_small.v:
- Added uart_sent flag to prevent UART retransmission
- Verified via Verilator: UART sends exactly one byte on halt
- Test byte: 0xAA (recognizable pattern)

research_stack_top.v:
- Auto-start logic (100ms after reset, no button needed)
- LED shows heartbeat when CPU running, register values on halt

research_stack_tangnano9k.cst:
- uart_tx=17, uart_rx=18 (matches Sparkle reference design)

Simulation results (Verilator):
- uart_test.v: 115 bytes in 300K cycles (continuous TX verified)
- research_stack_top: UART fires after Blitter halt, 0xAA byte sent
- LED pattern changes from IDLE to RUNNING to HALTED

2026-05-28 21:42:11 -05:00

Brandon Schneider

6a9fcdd115

fix: Blitter UART divisor 234→233 to match Lean uartBaudDivisor proof

Both now 115384 baud at 27MHz (within 0.16% of 115200).
Lean theorem uartBaudRateHz_within_1pct_of_115200 applies to both.

2026-05-28 16:36:37 -05:00

Brandon Schneider

468b449aad

feat: unified FPGA bitstream for Tang Nano 9K — BUILD SUCCESSFUL

research_stack_top.fs (2.0MB) — all modules synthesized:
- Blitter6502OISC (4K memory, SUBTLEQ CPU)
- q16_lut_core (Q16_16 arithmetic, 8 ops)
- blitter_memory_map (8-bit ↔ 32-bit bridge)
- voltage_mode_controller (4 BRAM modes)
- scale_space_bram (Gaussian kernel banks)
- highs_pivot_accelerator (simplex pipeline)

Timing: 195.92 MHz (PASS at 27 MHz target, 7.2x margin)
Device: GW1NR-LV9QN88PC6/I5 (Tang Nano 9K)

To flash: openFPGALoader -b tangnano9k research_stack_top.fs

2026-05-28 16:32:05 -05:00

3 commits