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Research-Stack/airtable_math_workloads.csv
Brandon Schneider e5fb0a5f4d chore: commit accumulated working tree changes 
Lean: update Semantics modules, add new numerics/physics data files
Hardware: update FPGA bitstreams (tangnano9k_uart_loopback)
Infra: k3s-flake tests, netcup-vps configuration, VCN compute substrate
Docs: ARCHITECTURE, specs, citation updates
2026-05-30 00:10:02 -05:00

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1Workload Name,Category,Best Substrate,Math Operations,Data Structure,Complexity Class,Parallelizability,Physical Grounding,Display Requirement,Lean Formalization,Status
2Menger Sponge QR,Fractal Geometry,MCU + USB-C SFP,XOR, bit shifts, addition,Menger lattice (N=64),O(n),Embarrassingly Parallel,Required,Optional,MengerSpongeFractalAddressing.lean,Specified
3GO Tile Flip,Game Theory,MCU + HDMI TMDS,Liberty check, capture detection, ko rule,Go board (19×19),O(n²),Highly Parallel,Optional,Required,TileStateMachine.lean,Specified
4Game of Life,Cellular Automata,MCU + DisplayPort,Birth/survival/death rules,2D grid (240×320),O(n),Embarrassingly Parallel,Optional,Required,GameOfLife_InformationTheory.md,Specified
5Soliton Fields,Soliton Fields,HDMI + DisplayPort,φ-phase, amplitude coefficients, velocity tensor,N-dimensional parameter matrix,O(n log n),Highly Parallel,Required,Required,VideoPhysics.lean,Specified
6Sidon Sets,Topology,MCU (SidonAVM),Greedy Erdős–Turán construction,Sidon set (max 8 elements),O(n²),Moderately Parallel,Not Applicable,Not Applicable,SidonAVM.lean,Deployed
7NetworkRAM Topology,Topology,PCIe Idle + Fiber,DriftTensor addressing, DelayLine slots,O(n),Highly Parallel,Required,Not Applicable,NetworkRAM.lean,Specified
8VCN 16D Field,Fractal Geometry,EPYC + VCN,16D coordinate projection,16D goxel field,O(n),Embarrassingly Parallel,Required,Optional,MeshRouting.lean,Specified