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453a366949
- Prover-Integrated Orchestration Layers (L0-L3): Goedel-Prover-V2 watchdog, BFS-Prover-V2 swarm consensus, bf4prover topology adaptation - FAMM Verilator benchmark: uniform vs preshaped delay comparison (4.4x speedup) - Swarm topological device prober: 11 agents probing traces, caps, delays, errors, vias, PDN - Spec sheet puller: 10 components with key params and topological relevance - Virtual FPGA system tests: 6/6 passed, 134K ops/s throughput - Fixed merge conflicts in AI-Newton test_experiment.ipynb
272 lines
6.9 KiB
Markdown
272 lines
6.9 KiB
Markdown
# Component Spec Sheet Reference
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**Generated:** 2026-05-06T23:04:52.050840
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## Components
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### U1_FPGA: GW1NR-LV9QN88PC6/I5
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- **Manufacturer:** Gowin Semiconductor
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- **Category:** FPGA
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- **Datasheet:** https://www.gowinsemi.com/en/support/datasheet/
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**Key Parameters:**
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- LUTs: 8640
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- FFs: 6480
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- BRAM: 468Kb (26 × 18Kb blocks)
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- DSP: 20 multipliers (16×16)
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- PLLs: 2
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- IO: 68 user I/O
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- Package: QFN88 (10×10mm)
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- Core voltage: 1.2V
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- IO voltage: 3.3V / 2.5V / 1.8V
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- Max frequency: ~200MHz (fabric), 400MHz (PLL out)
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- Flash: Embedded 64Mbit SPI
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- Programming: JTAG + SPI + UART
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**Topological Relevance:**
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- 8640 LUTs → partition into 11 agent compute units (785 LUTs each)
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- 20 DSP blocks → 20 parallel Q16.16 multiply-accumulate pipelines
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- 468Kb BRAM → 256 FAMM cells × 64-bit = 16Kb (fits in 1 BRAM block)
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- 2 PLLs → eigenvalue-derived clock distribution (τ ∝ 1/√λ)
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- 68 I/O → 8 HDMI + 32 DDR + 8 UART + 20 GPIO for topology sensing
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---
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### U2_DDR: MT41K128M16JT-125 (typical)
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- **Manufacturer:** Micron
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- **Category:** Memory
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- **Datasheet:** https://www.micron.com/products/dram/ddr3-sdram
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**Key Parameters:**
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- Density: 2Gb (128M×16)
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- Speed: DDR3-1600 (800MHz clock)
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- Data rate: 1600 MT/s
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- Burst length: 8
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- CAS latency: CL=11
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- tRCD: 13.75ns
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- tRP: 13.75ns
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- tRC: 48.75ns
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- Voltage: 1.5V (1.35V DDR3L)
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- Package: 96-ball FBGA
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- Row/Column: 14/10 addressing
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**Topological Relevance:**
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- 800MHz clock → 1250ps period → trace matching within 50ps = 4% tolerance
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- CL=11 → 13.75ns read latency → pipeline 11 stages in FPGA
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- Burst=8 → 8×16-bit = 128-bit FAMM data bus width
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- 1.5V → separate power plane with <5mΩ target impedance
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- tRC=48.75ns → 20.5M random accesses/sec → FAMM preshaping critical
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---
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### U3_OSC: SG-210STF 100.0000ML3 (typical)
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- **Manufacturer:** Epson
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- **Category:** Clock
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- **Datasheet:** https://www5.epsondevice.com/en/products/crystal_oscillator/
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**Key Parameters:**
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- Frequency: 100.000 MHz
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- Stability: ±50ppm
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- Jitter: <1ps RMS (12kHz-20MHz)
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- Rise/fall: <3ns
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- Output: LVCMOS
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- Voltage: 3.3V
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- Package: 2.5×2.0mm ceramic
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- Phase noise: -135dBc/Hz @ 10kHz offset
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**Topological Relevance:**
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- 100MHz → 10ns period → eigenvalue clock: λ_1→75ns, λ_16→45ns
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- ±50ppm → 5ns drift over 100k cycles → PLL lock required
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- <1ps jitter → suitable for Q16.16 timing precision (15ps LSB)
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- Phase noise -135dBc → clean enough for manifold clock distribution
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---
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### U4_REG: AMS1117-3.3 (typical)
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- **Manufacturer:** Advanced Monolithic Systems
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- **Category:** Power
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- **Datasheet:** https://www.advanced-monolithic.com/pdf/ds1117.pdf
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**Key Parameters:**
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- Output: 3.3V ±1.5%
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- Dropout: 1.1V @ 1A
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- Max current: 1A
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- Line regulation: 0.2% max
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- Load regulation: 0.4% max
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- Ripple rejection: 60dB @ 120Hz
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- Thermal shutdown: 165°C
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- Package: SOT-223
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**Topological Relevance:**
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- 1A max → 3.3W total → thermal topology: place near board edge
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- 60dB ripple rejection → 1000× noise reduction → clean analog rails
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- 165°C shutdown → thermal vias needed under package
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- 1.1V dropout → input must be >4.4V → 5V USB sufficient
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---
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### J1_HDMI: HDMI-A-19P-SMT (typical)
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- **Manufacturer:** Various (Molex, TE, Amphenol)
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- **Category:** Connector
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- **Datasheet:** https://www.hdmi.org/spec/index
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**Key Parameters:**
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- Pins: 19
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- TMDS pairs: 4 (3 data + 1 clock)
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- Impedance: 100Ω differential
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- Data rate: Up to 3.4Gbps per lane (HDMI 1.4)
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- Bandwidth: 10.2 Gbps total
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- DDC: I²C @ 100kHz
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- HPD: Hot plug detect (5V tolerant)
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- CEC: Consumer Electronics Control
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- Voltage: 5V @ 50mA (pin 18)
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**Topological Relevance:**
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- 100Ω differential → trace impedance must match within ±10%
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- 3.4Gbps → 294ps bit period → 15ps trace matching (5%)
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- 4 TMDS pairs → 4 parallel FAMM delay lines for video stream
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- DDC I²C → topology-aware EDID emulation for manifold display
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- HPD → topological hot-plug detection for swarm reconfiguration
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---
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### C1_C2_C4_100nF: GRM188R71H104KA93 (typical)
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- **Manufacturer:** Murata
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- **Category:** Passive
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- **Datasheet:** https://www.murata.com/en-us/products/capacitor/ceramiccapacitor
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**Key Parameters:**
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- Capacitance: 100nF ±10%
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- Dielectric: X7R
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- Voltage: 50V
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- ESR: <50mΩ @ 100MHz
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- ESL: ~0.5nH (0603)
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- SRF: ~22MHz
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- Package: 0603 (1.6×0.8mm)
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- Temp range: -55°C to +125°C
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**Topological Relevance:**
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- SRF 22MHz → effective decoupling to ~50MHz → covers FPGA core
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- ESL 0.5nH → via inductance dominates → minimize via length
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- X7R → ±15% over temp → account for in PDN impedance budget
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---
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### C3_10uF: GRM21BR61A106KE19 (typical)
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- **Manufacturer:** Murata
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- **Category:** Passive
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- **Datasheet:** https://www.murata.com/en-us/products/capacitor/ceramiccapacitor
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**Key Parameters:**
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- Capacitance: 10µF ±10%
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- Dielectric: X5R
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- Voltage: 10V
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- ESR: <10mΩ @ 1MHz
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- ESL: ~0.8nH (0805)
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- SRF: ~1.8MHz
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- Package: 0805 (2.0×1.25mm)
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- DC bias derating: -70% at 3.3V (effective ~3µF)
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**Topological Relevance:**
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- DC bias derating critical → effective 3µF not 10µF at 3.3V
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- SRF 1.8MHz → bulk decoupling below 10MHz → complements 100nF
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- ESR 10mΩ → low enough for PDN target <10mΩ with parallel caps
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---
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### C5_4u7: GRM21BR61C475KA88 (typical)
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- **Manufacturer:** Murata
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- **Category:** Passive
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- **Datasheet:** https://www.murata.com/en-us/products/capacitor/ceramiccapacitor
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**Key Parameters:**
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- Capacitance: 4.7µF ±10%
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- Dielectric: X5R
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- Voltage: 16V
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- ESR: <20mΩ @ 1MHz
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- ESL: ~0.8nH (0805)
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- SRF: ~2.6MHz
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- Package: 0805
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**Topological Relevance:**
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- LDO output cap → stability requirement: 4.7µF min for AMS1117
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- ESR 20mΩ → within LDO stable region (0.1-10Ω for most LDOs)
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---
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### PCB_TRACE: Standard 1oz Cu, 0.15mm width
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- **Manufacturer:** Generic
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- **Category:** PCB
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- **Datasheet:** N/A — standard IPC-2221
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**Key Parameters:**
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- Dielectric: FR-4 (εr=4.5 @ 1GHz)
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- Copper: 1oz (35µm)
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- Trace width: 0.15mm (6 mil)
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- Impedance: ~50Ω (microstrip, layer 1)
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- Delay: ~150ps/inch (6ps/mm)
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- Capacitance: ~1.1pF/cm
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- Inductance: ~3nH/cm
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- DC resistance: ~0.3Ω/cm (0.15mm, 1oz)
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- Min spacing: 0.15mm (6 mil)
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**Topological Relevance:**
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- 6ps/mm delay → 25mm trace = 150ps → matches DDR skew budget
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- εr=4.5 → impedance varies ±10% with manufacturing → calibrate per board
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- 0.3Ω/cm → 60mm power trace = 1.8Ω → unacceptable for PDN → use planes
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- FR-4 loss: ~0.02dB/mm @ 1GHz → 50mm = 1dB → negligible for <500MHz
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---
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### VIA: Standard IPC-2221 Type III
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- **Manufacturer:** Generic
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- **Category:** PCB
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- **Datasheet:** N/A — standard IPC-2221
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**Key Parameters:**
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- Drill: 0.3mm
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- Pad: 0.6mm
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- Antipad: 0.8mm
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- Inductance: ~0.8nH (1.6mm board)
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- Capacitance: ~0.5pF
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- Impedance: ~40Ω
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- Stub resonance: λ/4 @ ~25GHz for 1.6mm stub
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- Current capacity: ~1A (0.3mm, 1oz plating)
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**Topological Relevance:**
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- 0.8nH per via → 4 vias in PDN path = 3.2nH → limits decoupling above 100MHz
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- Stub at 1.6mm → resonance at 25GHz → safe below 5GHz → backdrill for HDMI
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- 0.5pF per via → negligible for <1GHz signals
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---
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