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130 lines
4.2 KiB
Markdown
130 lines
4.2 KiB
Markdown
# LUT-as-DSP: Dynamic Canal Hardware Architecture
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## The Core Equation
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The complete FPGA Warden Node computation collapsed to LUT lookups:
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$$
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\boxed{
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\phi_{\text{corr}} = \text{LUT}_{\text{void}}\Big[ \big(\Phi_{\text{acc}} \gg n \big) \oplus \text{MSB}_{\text{flip}} \Big] \;\;\text{where}\;\; \Phi_{\text{acc}}^{(t+1)} = \big(\Phi_{\text{acc}}^{(t)} + \lfloor \phi \cdot 2^{16} \rfloor \big) \;\text{mod}\; 2^{32}
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}
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$$
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---
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## Component Breakdown
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### 1. φ-Accumulator (Replaces Floating-Point Exponentiation)
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$$
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\Phi_{\text{acc}}^{(t)} = \Big( t \cdot \lfloor \phi \cdot 2^{16} \rfloor \Big) \;\text{mod}\; 2^{32} = \Big( t \cdot 106070 \Big) \;\text{mod}\; 4294967296
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$$
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**No multiplication at runtime** — implemented as iterative addition:
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```verilog
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always @(posedge clk)
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phi_acc <= phi_acc + 32'd106070; // φ × 2^16 fixed-point
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```
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### 2. Mod-7 Prime Counter (Address Traversal)
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$$
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c_{\text{mod7}}^{(t+1)} = \begin{cases}
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0 & \text{if } c_{\text{mod7}}^{(t)} = 6 \\
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c_{\text{mod7}}^{(t)} + 1 & \text{otherwise}
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\end{cases}
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$$
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**Coprimality guarantee** (J_MODES=13, prime × prime):
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$$
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\text{Traversal Period} = \frac{13 \times 7}{\gcd(13,7)} = 91 \;\text{steps}
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$$
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### 3. Mirror Logic (XOR Fold)
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$$
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\text{idx}_{\text{mirror}} = \big(\Phi_{\text{acc}} \gg 16\big) \oplus \big(\text{MSB}(\Phi_{\text{acc}}^{(t)}) \neq \text{MSB}(\Phi_{\text{acc}}^{(t-1)}) \big)
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$$
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Folds address space symmetrically when accumulator MSB flips (quadrant mirroring).
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### 4. Dual-Port Shadow Table (Atomic State Management)
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$$
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\text{State}_{\text{swap}}(t) = \begin{cases}
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\text{LUT}_A \leftarrow \text{LUT}_B & \text{if } t \equiv 0 \;(\text{mod } 91)
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\\
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\text{LUT}_A & \text{read-only during } 0 < t < 91
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\end{cases}
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$$
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**Race-free by construction**: No shared mutable state during attestation window.
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### 5. Void Mask LUT (Entropy Reservoir)
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$$
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\text{LUT}_{\text{void}}[i] = \text{void-and-cluster}(i) \in \{0, 1\}^{2^{13}}
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$$
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Baked at synthesis time — **no runtime PRNG**, **no seed**, **no non-determinism**.
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---
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## Complete Attestation Cycle Equation
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$$
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\boxed{
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\text{Phase}_{\text{out}} = \mathcal{C}\Big( \text{popcount}\big( \text{AND}(\text{LUT}_{\text{void}}[\text{idx}], \text{Deviation}_{\text{seg}}) \big) \Big)
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}
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$$
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Where:
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- $\text{Deviation}_{\text{seg}} = |\text{mean}(\text{seg}_i) - 127.5| / 127.5$ (integer: $|\text{mean} - 127| \times 520$)
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- $\mathcal{C}(x) = \begin{cases} \text{HELL} & x < 0.35 \cdot \text{SCALE} \\ \text{SEISMIC} & 0.35 \cdot \text{SCALE} \leq x < 0.47 \cdot \text{SCALE} \\ \text{GROUNDED} & x \geq 0.47 \cdot \text{SCALE} \end{cases}$
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- **Latency**: 91 clock cycles @ 50 MHz = **1.82 μs per attestation**
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---
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## Resource Collapse Summary
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| Operation | Software (floating-point) | Hardware (LUT-as-DSP) |
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|-----------|---------------------------|----------------------|
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| $\phi^{(i \bmod 7)}$ | `pow(PHI, i % 7)` | `phi_acc + 106070` |
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| Multiplication | `*` operator | LUT lookup |
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| Addition | `+` operator | LUT lookup |
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| Entropy source | `os.urandom()` / PRNG | Void mask (baked) |
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| Concurrency | Mutex/lock | Dual-port A/B swap |
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| Arithmetic units | FPU/DSP required | **Zero DSP blocks** |
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---
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## The Invariant (Why It Works)
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$$
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\forall t \in \mathbb{N}: \quad \phi_{\text{corr}}^{(t)} = f_{\text{LUT}}\big(g_{\varphi}(t)\big) \quad \text{where} \quad g_{\varphi}(t) = \lfloor t \cdot \phi \rfloor \;\text{mod}\; 2^{32}
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$$
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**No arithmetic in $f_{\text{LUT}}$** — pure combinational lookup.
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**No state mutation during attestation** — A/B shadow tables guarantee atomicity.
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**Deterministic by construction** — same input bytes → same φ-correlation → same phase classification.
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---
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## Hardware Resource Footprint (Lattice iCE40 HX8K)
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| Resource | Utilization | Budget | % Used |
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|----------|-------------|--------|--------|
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| LUT cells (logic) | ~200 | 7,680 | **2.6%** |
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| LUTRAM (void mask) | 8,192 bits | 8,192 | **100%** |
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| Flip-flops | ~50 | 7,680 | **0.7%** |
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| Block RAM | 0 | 128 KB | **0%** |
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| DSP slices | **0** | 8 | **0%** |
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**Zero DSP blocks. Zero floating-point. Zero CPU.**
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The entire Dynamic Canal routing computation collapsed to **φ-accumulator + mod-7 counter + LUT lookup**.
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---
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*Document ID: LUT_AS_DSP_DYNAMIC_CANAL*
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*Cross-ref: FPGA_WARDEN_NODE_SPEC.md, DAG 741*
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