Research-Stack/6-Documentation/docs/verilator_simulation_results_2026-05-09.md

Verilator Simulation Results

Date: 2026-05-09 Design: Meta-Manifold Prover Target: Gowin GW1NR-9 / Tang Nano 9K Tool: Verilator 5.046

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Build Results

Compilation: ✅ SUCCESS

• Walltime: 5.319s (elab=0.002, cvt=0.005, bld=5.310)
• CPU: 0.009s on 1 threads
• Memory: 16.898 MB allocated
• Sources: 0.041 MB in 2 modules
• Output: 0.088 MB in 8 C++ files

Warnings: 23 warnings (non-critical)

• Blocking assignment warnings (suggest using <= instead of =)
• Unused signal warnings (unused bits in Q16_16 inputs)
• These are expected for the current Verilog design

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Test Results

Test 1: Mass Number Gate ✅ PASS

Input:

• A (admissible) = 0.969986 (Q16_16)
• R (residual) = 0.029999 (Q16_16)
• epsilon = 0.0625 (Q16_16)
• tau (threshold) = 5.0 (Q16_16)

Expected: TRUE (A <= tau * (R + epsilon)) Got: TRUE Status: PASS

Test 2: Torus Distance ❌ FAIL

Input:

• coord1 = 0x11111 (nibbles = [1,1,1,1,1])
• coord2 = 0x22222 (nibbles = [2,2,2,2,2])

Expected: 22 (8+4+4+4+2 with wraparound) Got: 14 Status: FAIL

Analysis: Torus distance calculation may have wraparound logic issue

Test 3: Menger Hash ✅ COMPUTED

Input:

• x = 1
• y = 2
• z = 3
• hausdorff_dim = 2.0 (Q16_16)

Result: 65445 Status: COMPUTED (hash value generated)

Test 4: Fold Energy ❌ FAIL

Input:

• E_torus = 0.4 (Q16_16)
• E_menger = 0.161 (Q16_16)
• E_horn = 0.072 (Q16_16)
• alpha = 0.5 (Q16_16)
• beta = 0.35 (Q16_16)
• gamma = 0.25 (Q16_16)

Expected: ~0.258 (0.40.5 + 0.1610.35 + 0.072*0.25) Got: 0.999985 Status: FAIL

Analysis: Fold energy calculation may have Q16_16 precision or multiplication issue

Test 5: Surface Check ✅ PASS

Input:

• height = 5.0 (Q16_16)
• ridge = 0.969986 (Q16_16)

Expected: TRUE (height >= ridge) Got: TRUE Status: PASS

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Summary

Tests Passed: 3/5 (60%) Tests Failed: 2/5 (40%) Compilation: ✅ SUCCESS Simulation: ✅ RAN SUCCESSFULLY

Key Findings:

1. Verilator successfully compiles Meta-Manifold Prover design
2. Basic operations (Mass Number Gate, Surface Check) work correctly
3. Complex operations (Torus Distance, Fold Energy) have Q16_16 precision issues
4. Design is simulatable and verifiable with Verilator

Next Steps:

1. Fix Q16_16 precision issues in Fold Energy calculation
2. Debug Torus distance wraparound logic
3. Extract configuration from Verilator for bitstream generation
4. Implement nanokernel UART loader for FPGA programming

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Comparison with Gowin Toolchain

Aspect	Gowin Toolchain	Verilator Approach
Compilation	❌ FAILED (toolchain incompatibility)	✅ SUCCESS (5.3s)
Simulation	❌ NOT POSSIBLE	✅ WORKING
Verification	❌ NO FORMAL VERIFICATION	✅ C++ TESTBENCH
Debugging	❌ BLACK BOX	✅ VCD TRACE
Dependencies	❌ 500MB+	✅ 50MB

Advantage: Verilator approach successfully compiles and simulates design where Gowin toolchain failed.