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- Prover-Integrated Orchestration Layers (L0-L3): Goedel-Prover-V2 watchdog, BFS-Prover-V2 swarm consensus, bf4prover topology adaptation - FAMM Verilator benchmark: uniform vs preshaped delay comparison (4.4x speedup) - Swarm topological device prober: 11 agents probing traces, caps, delays, errors, vias, PDN - Spec sheet puller: 10 components with key params and topological relevance - Virtual FPGA system tests: 6/6 passed, 134K ops/s throughput - Fixed merge conflicts in AI-Newton test_experiment.ipynb
90 lines
5.2 KiB
Markdown
90 lines
5.2 KiB
Markdown
# Unified Signal Architecture — DisplayPort × Audio × FPGA
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**Status:** Architecture — bridges 3 deployed hardware pathways into one texel state machine
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**Deployed components:** HDMI shell, PipeWire waveprobe chain, DSP reconfiguration, braid DSP bridge
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## Architecture
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```
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┌──────────────────────────┐
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│ NUVMAP Texel Stream │
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│ (PIST → Cayley V4 → │
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│ braid/rope encoding) │
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└──────────┬───────────────┘
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│
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┌────────────────────┼────────────────────┐
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▼ ▼ ▼
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┌──────────────────┐ ┌──────────────────┐ ┌──────────────────┐
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│ DisplayPort │ │ PipeWire Audio │ │ FPGA Tang Nano 9K│
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│ 8K@60Hz │ │ 192kHz/24-bit │ │ 27MHz UART/BRAM │
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│ │ │ │ │ │
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│ Lane 0: φ-phase │ │ Left: TSM thermal │ │ V4 Cayley verify │
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│ Lane 1: Aₙ ampl │ │ Right: Waveprobe │ │ Mass preserved │
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│ Lane 2: vᵢⱼ tensor│ │ Center: GCL delta │ │ Triangle gate │
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│ Lane 3: witness │ │ │ │ Chiral state LED │
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│ │ │ VBLANK=SUBTRACT │ │ │
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│ NVENC session 0-7 │ │ HBLANK=PAUSE │ │ DAG-LUT burned │
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│ │ │ FRAME=ADD │ │ │
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│ HPD: ternary clock│ │ │ │ CEC: sync clock │
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└────────┬──────────┘ └────────┬──────────┘ └────────┬─────────┘
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│ │ │
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└──────────────────────┼──────────────────────┘
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│
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┌──────────▼───────────┐
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│ Unified Frame Sync │
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│ │
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│ DP VSYNC = audio │
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│ buffer swap │
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│ │
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│ Frame 0: keyframe + │
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│ full attestation │
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│ Frame N: delta only │
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│ │
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│ VBLANK: TVI samples │
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│ + audio FFT bins │
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│ HBLANK: mistake vecs │
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│ + GCL diff deltas │
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│ DDC: ZK-STARK proof │
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└───────────────────────┘
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```
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## Unified Timing
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| Signal | DP 8K60 | PipeWire Audio | FPGA |
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|--------|---------|---------------|------|
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| Period | 16.67ms | 5.21µs (192kHz) | 37ns (27MHz) |
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| Per frame | 33.18M texels | 3,200 samples | 450k cycles |
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| Blanking | VBLANK=45 lines | PAUSE buffer | DAG-LUT write |
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| Active | 4320 lines | ADD buffer | Cayley verify |
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| Sync | HPD Morse | Jack transport | CEC clock tick |
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## Deployed Verification
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| Component | File | Lines | Status |
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|-----------|------|-------|--------|
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| HDMI Computational Shell | `scripts/hdmi_computational_shell.py` | 301 | Deployed |
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| DP 8K60 Texel Spec | `docs/specs/DP_TEXEL_8K_ENCODING_SPEC.md` | 116 | Written |
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| PipeWire Waveprobe Chain | `tools-scripts/audio/pipewire_waveprobe_compression_chain.py` | 1,422 | Deployed |
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| DSP Reconfiguration | `scripts/execute_swarm_dsp_reconfiguration.py` | — | Deployed |
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| Braid DSP Bridge | `tools-scripts/braid/braid_dsp_bridge.py` | — | Deployed |
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| Hybrid DSP Test | `tools-scripts/testing/test_hybrid_dsp_deterministic.py` | — | Deployed |
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| V4 Cayley Verification | Lean 4 `CayleyFibergraph.lean` | — | Builds clean |
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| FPGA Invariant Scanner | `cff/fpga/bridge.py` + Verilog | — | Flashed + live |
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| GPU Eigenmass | `cff/gpu/eigenmass_engine.py` | — | CUDA 117ms |
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## Key Equation
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```
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Frame[t+1] = bind(
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Frame[t],
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{ DP_lane[0..3] → texel_stream,
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audio_left → waveprobe_score,
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audio_right → tsm_thermal,
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fpga_verify → V4_check },
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{ Δ_frame = H(DP_texels[t]) - H(DP_texels[t-1]),
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Δ_audio = |waveprobe[t] - waveprobe[t-1]|,
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gate = Δ_frame < τ_frame ∧ Δ_audio < τ_audio }
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)
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```
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The frame is admissible iff both the video texel entropy and audio waveprobe score remain within their Landauer thresholds. The FPGA V4 Cayley check is the hardware witness — if it fires a violation, the frame is quarantined via HPD Morse ABORT.
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