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2aef54d052
Lean: update Semantics modules, add new numerics/physics data files Hardware: update FPGA bitstreams (tangnano9k_uart_loopback) Infra: k3s-flake tests, netcup-vps configuration, VCN compute substrate Docs: ARCHITECTURE, specs, citation updates
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1.8 KiB
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9 lines
No EOL
1.8 KiB
CSV
Substrate Name,Category,Cost ($),Bandwidth,Math Complexity,Ops/$,Hardware Requirements,Status,Key Insight,Lean Formalization,Python Implementation
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TOSLINK Entropy,Physical Entropy,0,Physical noise,Simple (XOR/shifts),∞,TOSLINK transceiver + optical cable,Specified,Optical imperfections as deterministic stochastic channel,MechRouting.lean,vcn_compute_substrate.py
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USB-C to SFP + 1km Fiber,Physical Entropy,0,Physical noise,Simple (XOR/shifts),∞,USB-C to SFP adapter + 1km fiber spool,Specified,Hot-swappable SFP modules + fiber imperfections = modern optical entropy,MechRouting.lean,vcn_compute_substrate.py
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PCIe Idle Cycles,Harvested Cycles,0,~100MB/s DMA,Medium (Q0.16 scalar),∞,PCIe device with management controller,Specified,Link state machine idle cycles = free compute substrate,MeshRouting.lean,vcn_compute_substrate.py
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HDMI TMDS Abuse,Display Interface,0,~6GB/s (1080p@60),Complex (Soliton fields),∞,HDMI interface + TMDS access,Specified,Display cable as N-dimensional soliton field transport,MeshRouting.lean,hdmi_computational_shell.py
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DisplayPort Texel Stream,Display Interface,0,~32GB/s (8K@60),Complex (Soliton fields),∞,DisplayPort 1.4a + NVENC GPU,Specified,8K60 texel transport with NVENC acceleration,DP_TEXEL_8K_ENCODING_SPEC.md,dp_texel_encoder.py
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MCU (SidonAVM),Coordination,10,None,Medium (Q0.16 scalar),~100K,Raspberry Pi 2W or similar MCU,Deployed,AVM abstraction for Sidon set generation,SidonAVM.lean,sidon_avm.py
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FPGA Probing,Empirical Discovery,500,~1GB/s,Adaptive (Empirical),~1M,Tang Nano 9K + Xilinx FPGA,Specified,Empirical discovery of hardware capabilities via systematic probing,PROBING_NANOKERNEL_FPGA_ACCELERATOR.md,fpga_probing.py
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EPYC SP5 Fabric,Overkill,10000,~500GB/s,Very Complex (GPU fabric),580K,AMD EPYC SP5 + 96 cores,Theoretical,Treat silicon as unified compute fabric,NetworkedSelfSolvingSpace.lean,epyc_fabric.py |